1. Field of the Invention
The invention relates to a method of fabricating a semiconductor device, and more particularly, to a method of fabricating a storage node as well as a bit line contact of a dynamic random access memory (DRAM).
2. Description of the Related Art
FIG. 1 shows a structure of a DRAM cell fabricated by a conventional method. A substrate comprising an isolation region 13, a gate 12, a source region 11a and a drain region 11b is provided. On the isolation region 13, a metal wire 14 may also be formed. A dielectric layer 15 is formed over the substrate 10. The dielectric layer 15 is etched to form an opening exposing then source region 11a. A bit line 16 is then formed to couple the source region 11a. After the formation of the bit line 16, another dielectric layer 17 is formed on the dielectric layer 15. An opening is formed to penetrate through both the dielectric layers 17 and 15 to expose the drain region 11b. A storage node 18 is then formed to couple with the drain region 11b.
As shown in the figure, the storage node 18 is formed to penetrate through two dielectric layers 15 and 17. A relative high aspect ratio is thus resulted. As a consequence, the step coverage for filling the opening is poor. Therefore, a poor contact quality is obtained for the storage node. Furthermore, to have bit line and the storage node form on different surface level, an uneven topography is inevitable. In addition, the fabrication cost is relatively high.